1. Field of the Invention
The present invention relates to a method for evaluating (reliability testing) non-volatile memories such as FLASH memories. The invention particularly relates to a method for evaluating operation of such a non-volatile memory with respect to hot holes, and also to non-volatile memories with functions required to realize the present evaluation method.
2. Description of the Related Art
FIG. 8 is a block diagram showing a construction of a typical non-volatile memory (for example, a flash memory). The non-volatile memory 100 includes: a cell array 101 composed of a large number of memory cells 110 arranged in a matrix-like form; a word line selector 120, a write controller 130, a sense amplifier 140, a data selector 150, and a controller 160.
Here, each memory cell 110 includes a floating gate 111, a control gate (corresponding to gate terminal G), a source diffusion area (corresponding to source terminal S), and a drain diffusion area (corresponding to drain terminal D), all of these being formed on a semiconductor substrate. Further, between the floating gate 111 and the semiconductor substrate (not illustrated) is formed an oxide film thin enough to allow electrons to move into the floating gate 111 due to the tunnel phenomenon.
The word line selector 120 has an address decoder (not shown in FIG. 8; item 122 of FIG. 6) and is connected via word line 121 to gate terminal G of each memory cell 110 aligned in every row. In response to an address input, the word line selector 120 performs a decoding operation and selects/specifies a word line 121 that is connected to a target memory cell 110 to and from which data is to be written and read. The write controller 130, which is connected via a bit line 131 to drain terminal D of each memory cell 110 aligned in every column, controls data writing to a target memory cell 110. The sense amplifier 140 amplifies data signals read out from the memory cells 110; the data selector 150 selectively outputs the data signals amplified by the sense amplifier 140; the controller 160 controls operation of the write controller 130, the sense amplifier 140, and the data selector 150, in response to control signals received from an external apparatus.
A description will be made hereinbelow of the operation principle of each memory cell 110 of the non-volatile memory 100, referring to FIG. 9 and FIG. 10. FIG. 9 is a view for describing the operation principle of data writing to a memory cell 110; FIG. 10 is a view describing the operation principle of data erasing from a memory cell 110.
As shown in FIG. 9, for example, upon data writing to a memory cell 110, voltages of 10V, 5V, and 0V are applied to gate terminal G, drain terminal D, and source terminal S of the memory cell 110 via word line 121, bit line 131, and a source line, respectively, the floating gate 111 of the memory cell 110 being thereby charged with electrons (e−; hot electrons). In this manner, electrons (e−) stored in the floating gate 111 set the memory cell 110 to an OFF state, whereby data “0”, for example, is held therein. In contrast to this, without such electrons (e−) stored in the floating gate 111, the memory cell 110 is set to an ON state, whereby data “1”, for example, is held therein.
As shown in FIG. 10, when erasing data stored in the memory cell 110 (when removing electrons stored in the floating gate 111), voltages of 0V and 10V are applied to the gate terminal G and the drain terminal D of the memory cell 110 via the word line 121 and the bit line 131, respectively, the electrons (e−) being thereby removed from the floating gate 111.
When such an evaluation (reliability test) of a non-volatile memory 100, or more precisely, evaluation of its data retention property, is performed, it is necessary to consider that loss of electron charge in the floating gate 111 increases with time. Therefore, when such a non-volatile memory 100 is tested at shipment by manufacturers or at installation by users, the loss (electric charge leak resulting from defects in floating gate films, particles, and so on) is accelerated in some way to evaluate or screen the data retention property in a short time. Generally speaking, the electric charge leak is accelerated with higher atmospheric temperatures. Hence, on the basis of this principle, the acceleration is performed by exposing the non-volatile memory 100 to high temperatures or performing an operation test of the non-volatile memory 100 at high temperatures (for example, Japanese Patent Number 2865456 and Japanese Patent Application Publication Number 2000-13 1398).
In the field of non-volatile memories, the following new fault mode (phenomenon) has been recently discovered. When a non-volatile memory 100 is subjected to write/erase operations with a high voltage applied thereto, holes (e+), so-called hot holes, are trapped in an oxide film under the floating gate 111 as shown in FIG. 11, and such hot holes serve as media that neutralizes the floating gate 111 by removing the electrons stored therein. More precisely, at the time of programming (or data erasing), hot holes (e+) concentrating between the floating gate 111 and the drain capture electric charge (e−) stored in the floating gate 111, whereby the electric charge is removed, so that the logic held in the memory cell 110 is resultantly inversed.
The following are three possible causes of such a phenomenon. Firstly, programming potentials higher than design specifications caused by manufacture variations or any other reasons enhance generation of hot holes (e+). Secondly, a high voltage applied by the word line 121 to the source or the drain enhances neutralization of electric charge (e−) stored in the floating gate 111, which neutralization is caused by hot holes (e+). Thirdly, the floating gate 111 downsized with recent downsizing of the non-volatile memory 100 (memory cell 110) can only store a reduced amount of electric charge (e−), so that the floating gate 111 is even more susceptible to the effects of hot holes (e+).
This newly discovered fault mode necessitates evaluation of operation of a non-volatile memory 100 with respect to hot holes (e+). However, in an attempt to accelerate the phenomenon with heat to evaluate the operation using the foregoing common evaluation method for data retention property, hot holes (e+) are diffused and withdrawn, so it is impossible to evaluate the operation of the non-volatile memory 100 with respect to hot holes. Generally speaking, after exposing a non-volatile memory to a 125° C. atmosphere for 168 hours, hot holes vanish completely, and thus the phenomena due to hot holes cannot be detected at all. Japanese Patent Number 2865456, Japanese Patent Application Publication Number 2000-131398, and Japanese Patent Application Publication Number HEI5-205491 disclose techniques relating to non-volatile memory tests, but none of them disclose anything about a method for evaluating operation of a non-volatile memory with respect to hot holes.
Accordingly, current techniques, if used in the operation evaluation with respect to hot holes, will necessitate real time evaluation. For example, it takes three whole years to evaluate a 3-year-span phenomenon in which an electric charge leaks gradually for three years before gargled data (logic inversion) is eventually caused. In such a situation, a technique of generating an increased number of hot holes is desired so as to speed up the evaluation of operation of a non-volatile memory with respect to hot holes.